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STM32MP1 support available in SW4STM32

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APSR (Application Processor Status Register)

Hi Ayoub,

The code runs each seconds and sometimes I get this behavior (once a day, once a week).
In the case of the breakpoint s14=50 s15=4.1366
vcmpe s15, s14 should set the flags based on s15-s14 which gives a negative value so the N flag=1
but the ble (branch if Less or Equal) does not jump confirmed by the APSR bits 28 to 31 = 0
so the vcmpe has not set the flag or the flag has disapeared for unknown reason that I try to understand

Best regards

France


First ,you can check the bit 31 in the FPSCR after the execution of the vmcpe (in the assembly view)
vmcpe set the flags in the FPSCR and after copy the values NZCV to APSR.

Second, you can use the Instruction Synchronization Barrier (ISB --> __ISB()) to flush the pipeline in the processor so that all instructions following the ISB are fetched from cache or memory after the instruction has completed. It ensures that the effects of context altering operations and any branches that appear in program order after it (the ISB) are always written into the branch prediction logic with the context that is visible after the ISB instruction (this will ensure correct execution of the instruction stream)

Best regards,
Ayoub
AC6

Thanks Ayoub,

This is random and seldom, so 99.9999% the flags will be set correctly by the vmcpe.
All my code is C or C++.
the original code was
if (m_fCoor_I > 50.0F)
m_fCoor_I = 50.0F;
does it means I need to integrate the __ISB() instruction before each floating point comparaisons because I have many.

As a workaround I modified to have the comparison in integer
long int lCorr = m_fCorr_I;
if (lCorr > 50)
m_fCorr_I=50.0F;

Best regards