Loading...
 

SW4STM32 and SW4Linux fully supports the STM32MP1 asymmetric multicore Cortex/A7+M4 MPUs

   With System Workbench for Linux, Embedded Linux on the STM32MP1 family of MPUs from ST was never as simple to build and maintain, even for newcomers in the Linux world.
And, if you install System Workbench for Linux in System Workbench for STM32 you can seamlessly develop and debug asymmetric applications running partly on Linux, partly on the Cortex-M4.
You can get more information from the ac6-tools website and download two short videos (registration required) highlighting:

System Workbench for STM32


You are viewing a reply to ADC pin Current Draw  

ADC pin Current Draw

I don’t have the datasheet for the F103 handy, but here’s some data taken from the F072 datasheet, which I suspect applies to all STM32’s with ADC’s.

Section 6.3.16, from table 58, STM32F072 datasheet (DocID025004 Rev 2)

Sampling switch resistance: 1K
Internal sample and hold capacitor: 8 pF

Worst-case peak current draw will be:
Ipeak = Vin / 1K
If Vin = 3.3V, Iin(peak) will be 3.3 / 1000 ~= 3.3mA

This is the worst-case peak current, it assumes that the internal sampling capacitor is fully discharged (close to AVss) and your signal source (Vin) is at the upper analog rail (AVdd). As the sampling cap charges (or discharges) to the level applied to the analog input, the current will of course decrease and eventually approach 0.

The actual formula for peak current draw takes into account the voltage level across the internal sampling capacitor:

Ipeak = (Vin - Vcap) / 1K

Vin = Voltage applied to analog input pin
Vcap = Voltage across internal sampling capacitor just before input is sampled. This will be at or close to the level of the last analog input that was converted.

Actual current draw can be positive or negative depending on the voltage level that the internal sampling capacitor is sitting at, and what the signal level applied to the analog input is when the analog mux switches the pin onto the sampling cap.

Ideally, analog signal sources provided to an ADC input (for any device that uses a sample-and-hold type of signal capture) should be as low impedance as possible. A high-impedance signal source can be used only if you’re willing to specify a lengthy sampling period. All STM32 ADCs provide a means to set the input sampling period. I would not suggest using the minimum sampling period unless your signal impedance is very low (< 270 ohms).

I recall seeing somewhere, in one of the ST reference documents (I regret to say I don’t remember which one) a table showing recommended signal impedance for differing ADC clock rates and sample period selections. The 270 ohm figure mentioned above is one value I remember seeing in that table.