Just one precision to my previous message: To be sure flash memory prefetch and caching is enabled, check the FLASH_ACR register; there are 3 bits significant in this case:
- ICEN - Instruction Cache Enable, that enables an (64 lines of 16 bytes) instruction cache in front of the flash
- DCEN - Data cache Enable, that enables caching up to 8 lines of 64 bytes for data access to the flash (for accessing data pools for example)
- PRFTEN - Prefetch Enable, that enables prefetching instructions
These bit are not set on reset, but may be set by firmware initialization; if they are not you should set them in your own code to benefit from these... But don’t forget to reset the caches before enabling them (by setting DCRST and ICRST in the same register); be careful *not* to change the flash latency that will have been set by the firmware when raising the CPU frequency.
Hope this helps,