Loading...
 

STM32MP1 support available in SW4STM32

   With System Workbench for Linux, Embedded Linux on the STM32MP1 family of MPUs from ST was never as simple to build and maintain, even for newcomers in the Linux world.
And, if you install System Workbench for Linux in System Workbench for STM32 you can seamlessly develop and debug asymmetric applications running partly on Linux, partly on the Cortex-M4; you can download a short video showcasing this on the ac6-tools website (registration required).

System Workbench for STM32


verify failed after enabling 32KB SRAM2 for STM32L476RG

Hi All,

I’m using STM32L476RG-Nucleo, AC6 IDE generated linker script only offers 96 KB RAM.
My need application more RAM, can I use 32 KB which is SRAM2 as below.

MEMORY
{
FLASH (rx)  : ORIGIN = 0x8000000, LENGTH = 1024K
RAM (xrw)  : ORIGIN = 0x20000000, LENGTH = 96K
RAM_2 (xrw)  : ORIGIN = 0x10000000, LENGTH = 32K
}

and

.ram2_bss :
{
. = ALIGN(4);

  • (.ram2_bss)
  • (.ram2_bss*)


} >RAM_2

I am getting verification failure, Can any one help to analyze below failure issues.


Open On-Chip Debugger 0.10.0-dev-00275-gd486ac2-dirty (2017-03-06-15:13)
Licensed under GNU GPL v2
For bug reports, read
http://openocd.org/doc/doxygen/bugs.html
Info : The selected transport took over low-level target control. The results might differ compared to plain JTAG/SWD
padded zone erase set to 1
adapter_nsrst_delay: 100
srst_only separate srst_nogate srst_open_drain connect_assert_srst
adapter speed: 1800 kHz
Info : clock speed 1800 kHz
Info : STLINK v2 JTAG v28 API v2 M v17 VID 0x0483 PID 0x374B
Info : using stlink api v2
Info : Target voltage: 3.261297
Info : STM32L476.cpu: hardware has 6 breakpoints, 4 watchpoints
adapter speed: 240 kHz
STM32L476.cpu: target state: halted
target halted due to debug-request, current mode: Thread
xPSR: 0x01000000 pc: 0x080367b4 msp: 0x20018000
Info : Unable to match requested speed 8000 kHz, using 4000 kHz
Info : Unable to match requested speed 8000 kHz, using 4000 kHz
adapter speed: 4000 kHz

    • Programming Started **

auto erase enabled
Info : Device id = 0x10076415
Info : STM32L4xx flash size is 1024kb, base address is 0x8000000
Info : Erase the padded zone before the write
Error: Whole bank access must start at beginning of bank.
STM32L476.cpu: target state: halted
target halted due to breakpoint, current mode: Thread
xPSR: 0x21000000 pc: 0x20000068 msp: 0x20018000
Warn : no flash bank found for address 10000000
wrote 294912 bytes from file Debug/freeRTOS-8.2.3.elf in 6.979435s (41.264 KiB/s)

    • Programming Finished **
    • Verify Started **

STM32L476.cpu: target state: halted
target halted due to breakpoint, current mode: Thread
xPSR: 0x61000000 pc: 0x2000002e msp: 0x20018000
STM32L476.cpu: target state: halted
target halted due to breakpoint, current mode: Thread
xPSR: 0x61000000 pc: 0x2000002e msp: 0x20018000
STM32L476.cpu: target state: halted
target halted due to breakpoint, current mode: Thread
xPSR: 0x61000000 pc: 0x2000002e msp: 0x20018000
Error: checksum mismatch - attempting binary compare
diff 0 address 0x10000000. Was 0xeb instead of 0x00
diff 1 address 0x10000002. Was 0x90 instead of 0x00
diff 2 address 0x10000003. Was 0x46 instead of 0x00
diff 3 address 0x10000004. Was 0x72 instead of 0x00
diff 4 address 0x10000005. Was 0x65 instead of 0x00
diff 5 address 0x10000006. Was 0x65 instead of 0x00
diff 6 address 0x10000007. Was 0x52 instead of 0x00
diff 7 address 0x10000008. Was 0x54 instead of 0x00
diff 8 address 0x10000009. Was 0x4f instead of 0x00
diff 9 address 0x1000000a. Was 0x53 instead of 0x00
diff 10 address 0x1000000c. Was 0x02 instead of 0x00
diff 11 address 0x1000000d. Was 0x01 instead of 0x00
diff 12 address 0x1000000e. Was 0x01 instead of 0x00
diff 13 address 0x10000010. Was 0x02 instead of 0x00
diff 14 address 0x10000011. Was 0x80 instead of 0x00
diff 15 address 0x10000015. Was 0xf8 instead of 0x00
diff 16 address 0x10000016. Was 0x01 instead of 0x00
diff 17 address 0x10000018. Was 0x3f instead of 0x00
diff 18 address 0x1000001a. Was 0xff instead of 0x00
diff 19 address 0x10000020. Was 0x32 instead of 0x00
diff 20 address 0x10000026. Was 0x29 instead of 0x00
diff 21 address 0x10000027. Was 0xcf instead of 0x00
diff 22 address 0x10000028. Was 0x8c instead of 0x00
diff 23 address 0x10000029. Was 0xbd instead of 0x00
diff 24 address 0x1000002a. Was 0xf4 instead of 0x00
diff 25 address 0x1000002b. Was 0x4d instead of 0x00
diff 26 address 0x1000002c. Was 0x59 instead of 0x00
diff 27 address 0x1000002d. Was 0x20 instead of 0x00
diff 28 address 0x1000002e. Was 0x4e instead of 0x00
diff 29 address 0x1000002f. Was 0x41 instead of 0x00
diff 30 address 0x10000030. Was 0x4d instead of 0x00
diff 31 address 0x10000031. Was 0x45 instead of 0x00
diff 32 address 0x10000032. Was 0x20 instead of 0x00
diff 33 address 0x10000033. Was 0x20 instead of 0x00
diff 34 address 0x10000034. Was 0x20 instead of 0x00
diff 35 address 0x10000035. Was 0x20 instead of 0x00
diff 36 address 0x10000036. Was 0x46 instead of 0x00
diff 37 address 0x10000037. Was 0x41 instead of 0x00
diff 38 address 0x10000038. Was 0x54 instead of 0x00
diff 39 address 0x10000039. Was 0x31 instead of 0x00
diff 40 address 0x1000003a. Was 0x36 instead of 0x00
diff 41 address 0x1000003b. Was 0x20 instead of 0x00
diff 42 address 0x1000003c. Was 0x20 instead of 0x00
diff 43 address 0x1000003d. Was 0x20 instead of 0x00
diff 44 address 0x100001fe. Was 0x55 instead of 0x00
diff 45 address 0x100001ff. Was 0xaa instead of 0x00
diff 46 address 0x10000200. Was 0xf8 instead of 0x00
diff 47 address 0x10000201. Was 0xff instead of 0x00
diff 48 address 0x10000202. Was 0xff instead of 0x00
diff 49 address 0x10000203. Was 0xff instead of 0x00
diff 50 address 0x10000400. Was 0xf8 instead of 0x00
diff 51 address 0x10000401. Was 0xff instead of 0x00
diff 52 address 0x10000402. Was 0xff instead of 0x00
diff 53 address 0x10000403. Was 0xff instead of 0x00
diff 54 address 0x10000600. Was 0x4d instead of 0x00
diff 55 address 0x10000601. Was 0x59 instead of 0x00
diff 56 address 0x10000602. Was 0x5f instead of 0x00
diff 57 address 0x10000603. Was 0x44 instead of 0x00
diff 58 address 0x10000604. Was 0x49 instead of 0x00
diff 59 address 0x10000605. Was 0x53 instead of 0x00
diff 60 address 0x10000606. Was 0x4b instead of 0x00
diff 61 address 0x10000607. Was 0x20 instead of 0x00
diff 62 address 0x10000608. Was 0x20 instead of 0x00
diff 63 address 0x10000609. Was 0x20 instead of 0x00
diff 64 address 0x1000060a. Was 0x20 instead of 0x00
diff 65 address 0x1000060b. Was 0x08 instead of 0x00
diff 66 address 0x10000618. Was 0x21 instead of 0x00
diff 67 address 0x10000619. Was 0xec instead of 0x00
No more differences found.

    • Verify Failed **

shutdown command invoked

Hi sachingole,
did you find the problem?
I have the same problem with enabling the TCM-Ram on STM32F767, although i added the fill zero loop to the startup file.
Does anyone know the solution to this problem?
Thanks.

Hi Daniel,

Problem is not solved, I get same error again.

However program get flashed and it work as expected.

Let me know if you got solution.

Best regards,
sachin


Hi sachin,
I think it’s a Problem with the run configuration, because I don’t get any problems during transfer using the debugger.
Though, up to know I didn’t find a solution.
Kind regards,
daniel


Hi,

I use SRAM section definition as defined at hereQuestion then verification errors were disappeared.

Regards,
ierturk


Hi sachin,
I think it’s a Problem with the run configuration, because I don’t get any problems during transfer using the debugger.
Though, up to know I didn’t find a solution.
Kind regards,
daniel